Progress in Z-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage
نویسندگان
چکیده
In this paper, we extend our studies on the use of zero impact ionization and zero subthreshold swing field-effect-transistor (Z-FET) as a capacitor-less one-transistor dynamic random access memory (1TDRAM) through both experiment and TCAD simulation. The data retention time is measured as a function of biasing, temperature and device dimensions, leading to a simple predictive model. An alternative writing method using the source MOSFET is presented, which is potentially more compatible with the conventional DRAM array design. The operation of a Z-FET memory array is discussed, in which the write and read signals are adapted from the single cell to achieve selective operation. Finally, we present simulations demonstrating that the Z-FET can be used to store multiple bits thanks to the charges on both the top and bottom gate capacitors. 2013 Elsevier Ltd. All rights reserved.
منابع مشابه
The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure ...
متن کاملNovel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time
A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and >...
متن کاملZ-FET as capacitor-less eDRAM cell for high density integration
2D numerical simulations are used to demonstrate the Z-FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption ...
متن کاملA DRAM based Physical Unclonable Function Capable of Generating >10 Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication
A DRAM based Physical Unclonable Function (PUF) utilizing the location of weak retention cells is demonstrated in 65nm CMOS. A new authentication scheme is proposed for the DRAM PUF where a random pattern is written to a small section of the DRAM and then retention failures are induced. To further increase the number of Challenge Response Pairs (CPRs), the data pattern including retention failu...
متن کاملA systematic study of the sharp-switching Z-FET device: From mechanism to modeling and compact memory applications
This paper presents a systematic study of a sharp-switching device built in fully-depleted silicon-oninsulator (FD-SOI) that we have called Z-FET, as it features zero subthreshold swing (<1 mV/decade of current) and zero impact ionization. The Z-FET is a compact device with a single front gate that experimentally demonstrates a current ION/IOFF ratio >10 at low supply voltage, as well as gate-c...
متن کامل